The present invention relates generally to methods for fabricating integrated circuits using metal oxide semiconductor (MOS) technology. More particularly, the present invention relates to MOS devices with a gate width of less than 0.3 micron.
Metal oxide semiconductors are well known in the art. With the rapid integration of elements in the device, the thickness of the silicon oxide gate dielectric layer has approached the 2 nm thickness level. Such thin gate oxide layers require stringent protocols during fabrication especially in the gate etching process. In addition, concomitant with this reduction in the thickness of the gate oxide layer is the device""s high leakage current caused by direct tunneling effects.
Shinriki et. al., U.S. Pat. No. 5,292,673 describes a MOSFET that contains a tantalum pentoxide gate insulating film. Although the patent asserts that the device exhibits improved electrical characteristics, nevertheless, it is believed that the device suffers from, among other things, high leakage currents because of the silicon oxide layer, which is formed by reoxidation between the tantalum pentoxide gate insulating film and the silicon substrate, has defects including non-uniformity.
The present invention is based in part on the recognition that employing a gate dielectric layer formed at least in part from a high dielectric constant material comprising Ta2O5 will significantly improve the performance of the MOS device by, among other things, reducing or eliminating the current leakage associated with prior art devices.
Accordingly, in one aspect the invention is directed to a method for fabricating an MOS device having a gate width of less than 0.3 micron that includes the steps of:
(a) forming an interfacial layer on a semiconductor substrate of a first conductive type wherein the interfacial layer is preferably sufficiently thin to limit parasitic capacitance of the device;
(b) forming a high dielectric constant layer on the interfacial layer that comprises a material that is selected from the group consisting of Ta2O5, Ta2(O1xe2x88x92xNx)5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta2O5)rxe2x80x94(TiO2)1xe2x88x92r wherein r ranges from about 0.9 to less than 1, a solid solution (Ta2O5)sxe2x80x94(Al2O3)1xe2x88x92s wherein s ranges from 0.9 to less than 1, a solid solution of (Ta2O5)txe2x80x94(ZrO2)1xe2x88x92t wherein t ranges from about 0.9 to less than 1, a solid solution of (Ta2O5)uxe2x80x94(HfO2)1xe2x88x92u wherein u ranges from about 0.9 to less than 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate;
(c) depositing a layer of electrically conductive material on the high dielectric constant layer;
(d) selectively removing portions of the layer of electrically conductive material to form a gate electrode and to expose portions of the high dielectric constant layer;
(e) implanting impurity ions through the exposed portions of the high dielectric constant layer into the substrate to form source and drain regions of a second conductive type;
(f) forming first spacers that are adjacent the gate electrode and cover portions of the source and drain regions of the second conductive type;
(g) removing the exposed portions of the high dielectric constant layer;
(h) implanting a second dose of impurity ions into the source and drain regions;
(i) depositing a layer of insulator material over the surface of the device, wherein the layer of insulator material may have an irregular surface;
(j) optionally, planarizing the surface of the insulator material;
(k) removing portions of the insulator material to form contact holes in the insulator material that are in communication with the source and drain regions; and
(l) filling the contact holes with contact material.
In preferred embodiments, the electrically conductive material comprises metal that is selected from the group consisting of TiN, W, Ta, Mo and mixtures thereof. Alternatively, the electrically conductive material comprises doped polysilicon.
In another embodiment the method includes the step of forming second spacers that are adjacent the first spacers and cover portions of the source and drain regions following step (g) and before step (h) and/or the step of forming a silicide layer on the source and drain regions following step (h).
In another aspect, the invention is directed to an MOS transistor formed on a semiconductor substrate of a first conductivity type that includes:
(a) an interfacial layer formed on the substrate;
(b) a high dielectric constant layer covering the interfacial layer that comprises a material that is selected from the group consisting of Ta2O5, Ta2(O1xe2x88x92xNx)5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta2O5)rxe2x80x94(TiO2)1xe2x88x92r wherein r ranges from about 0.9 to less than 1, a solid solution (Ta2O5)sxe2x80x94(Al2O3)1xe2x88x92s wherein s ranges from 0.9 to less than 1, a solid solution of (Ta2O5)txe2x80x94(ZrO2)1xe2x88x92t wherein t ranges from about 0.9 to less than 1, a solid solution of (Ta2O5)uxe2x80x94(HfO2)1xe2x88x92u wherein u ranges from about 0.9 to less than 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate;
(c) a gate electrode having a width of less than 0.3 micron covering the high dielectric constant layer;
(d) first and second lightly doped regions of a second conductivity type disposed on respective areas of the substrate surface;
(e) a source and drain regions of the second conductivity type; and
(f) a pair of spacers formed adjacent to the gate electrode and formed on the high dielectric constant layer.
In a preferred embodiment, the MOS transistor also includes an insulator layer covering the device and defining a first contact hole that is filled with a first contact material and a second contact hole that are filled with a second contact material, wherein the insulator layer has a substantially planar surface.